Five decisions, four of the simulation's changes, one re-route. Decided: XT30 for the bus; a reset brakes; SimpleFOC; VMOT down to 12 V; and no enclosure fins — the drive runs below its peak current and 20 A becomes a burst to measure on the prototype. On board A, the low side's via array is under a tab of the switch-node pour on B.Cu, so all sixteen barrels carry current rather than four; the high side has a fifth row of barrels, twenty in all, which is the most the drain pad and the shunts' courtyards on the back allow; an unfitted 2.2 Ω + 470 pF snubber sits under each high side; both input pulls of every driver go to GND; and the magnet is Ø6. Freerouting finished in its first round again: 1361 segments, 278 vias, DRC, ERC and the netlist diff clean.

The simulation's conduction solver, re-run on the routed board in a scratch copy, is the honest check: the busiest low-side barrel falls from 5.16 to 2.82 A rms and the busiest high-side one from 2.42 to 2.10, both still over the 2 A guideline at a continuous 20 A because the current crowds toward the shunts, and both under it below about 14 A RMS. Two consequences for board B came with the decisions: the gate rail has to stay on through a reset, or the brake lasts only as long as its capacitors; and a 20 V PD contract could back-drive a lower-voltage pack, which is answered by not using the two together — PD replaces a pack.

The electromagnetic simulation, ten phases. sim/ solves the board rather than estimating it: FastHenry on the copper as routed, FastCap for the sense taps, ngspice for the edges, openEMS full wave as a cross-check, plus the encoder field and the thermal path. Fourteen questions, twenty-four findings, four hypotheses — all four confirmed or resolved. Three answers change the design's own arithmetic: the commutation loop is 2.06 nH where geometry.commutation_loop() says 0.39, because VBUS reaches the high-side drain from In2 through a sixteen-via field rather than from a plane 0.1 mm away; twelve of those sixteen vias under each low-side drain are islands on B.Cu and carry nothing; and the DC-link ceramics are worth 5.5–9.7 µF of their 13.2 µF marking at 60 V. One number the board cannot settle decides several of the others — how hard the EG2103's output stage drives, which its only obtainable document gives without a test condition: 62.6 V of V_ds and no snubber at the datasheet reading, 73.9 V and a 145 MHz ring at a strong output stage.

P7 was rebuilt, and the disagreement turned out to be the model. openEMS first returned 3.82 nH against FastHenry's 2.06 and it was recorded as a solver disagreement. It was five defects in the full-wave model: the conducting FETs were cylinders about an axis lying in F.Cu, which is 0.1525 mm above In1, so each rod cut about 1 mm² out of the ground plane and the high-side one shorted VBUS to GND at the drain; a port box sized from pad centres bit into the copper and none of its four coordinates survived the mesh merge; the excitation was a Gaussian centred at 750 MHz while the answer was read at 30–200 MHz; a band mean folded the loop's own 399 MHz resonance into “inductance”; and an unscaled ω² against a 1e8 intercept returned 1e36 nH. Fixed, the cross-check agrees to 8.5 % — 2.91 nH de-embedded against 2.68. There are no nets in FDTD, only metal: two conductors inside one cell are one conductor, and a mesh that looks converged can be converged on the wrong topology, which this one was twice on the way up.

Nothing in sim/ applies any of it. The hand-back list is fourteen proposed changes and six findings still open, all of them above.

A copper viewer on this page. tools/plot_layers.py exports one SVG per layer with kicad-cli, all on the same board-area page so they land in register, then crops every one of them to the outline's own box and repaints the drill holes in the plate colour so a hole reads as a hole. It also reads the board for what the panel says — tracks, copper length, pads, pour nets, vias — and writes layers.json, which is the only thing the viewer knows about the board: add a layer and the page follows. The four static layer figures are gone; the stack, the grid and a 16× zoom replace them, and the cursor reads out in the radius and angle the floorplan is written in. gen_boards.py and route.py both re-run it, so the page cannot show yesterday's copper.

Board A routed, all of it. 1351 track segments, 283 vias, nothing unconnected, DRC and ERC clean, the heatsink land clear. The first routed board had made 69 of 170 connections and blamed the driver ring; measured, nearly every open connection ended at the RP2350, which had no room to fan out — a 0.4 mm-pitch QFN needs four staggered rows of vias, 2.9 mm deep, and the chip had 0.3 mm. The CPU wedge was rebuilt around that band, the FETs turned so their gates face the driver row instead of the heatsink land, the sense row rearranged for arcs, the shunts moved under the switch-node island so every 20 A pad takes a via, and the regulator cluster copied from Raspberry Pi's RP-006440 reference to the 0.05 mm — which found the bootstrap diode backwards, VREG_AVDD tied straight to 3V3, and no USB series resistors.

Then the router was measured rather than trusted, some of it by reading its bytecode. Freerouting joins a wire to a pad only if the wire ends on the pad's centre to the 0.1 µm; it cannot leave a fine-pitch pad that is not on the 45° grid; a protected wire is something it cannot tee into and, joined twice, something it normalises for ever; and its last pass can undo its earlier ones. So a new tools/fanout.py makes the copper it does badly — the QFN escape, the gate and sense arcs, the escapes, the plane taps — as locked tracks, and route.py hands the router vias instead of stubs and takes every finished net away from it.

That got to three open connections and stuck there, whichever router or order was used — which is the shape of a capacity limit, not of a search. It was: the escape vias sat in four rows 0.71 mm apart, and a 0.15 mm track passing radially between two rows needs 0.23 to clear a via pad, 0.15 of clearance and half its own width on each side, so 0.91 mm. There was no radial lane anywhere in the field. Pushing the outermost row alone out by 0.20 mm buys one the whole way round the chip for 0.2 mm of depth; with that, and a second try at the one pin the planned rows could not place, freerouting finished the board in its first round. Also new: tools/finish.py, a maze router over the board's rasterised free space, which closed connections when the board was still short of them and now has nothing to do.

Phase cells in from 70° to 60°, using the channel interior to the screws. A cell is short of angle, not area, and angle costs radius: a millimetre of arc at R 20 is 2.9°, the same millimetre at R 29.5 is 1.9°. The cell was 70° because small parts sat at small radius — a 1 µF 0805 beside the gate driver took 30° on its own, while both MOSFETs together needed 18. The band the six boss pads sit on is empty between them, so the bootstrap diode, the DC-link 100 n, both input pulls and each phase's clamp diode moved out there at R 29.3, and the DC-link bulk to its own row at R 26.8.

Three consolidations paid for it: one 4.7 µF at the power link instead of a 1 µF per driver, the lead pad narrowed to ±7°, and the row packer taught to dodge parts in other rows. The result was 60/60 — which put the six bolts back on an even circle, the thing grouping the phases had cost.

Routing later took most of it back. A part in a phase cell's channel can only be connected if its nets are GND or the phase output: the phase-output pour owns B.Cu beneath it, the heatsink land owns F.Cu above it, and the bosses cut the outer ring into six arcs. Five of the six parts per cell came back in and the cells widened to 68°, which costs the even bolt circle and buys 29 mm² of heatsink land. Only the clamp diode stayed out there.

One methodological note, because it nearly produced a wrong answer: the first sweep said the cells would come down to 50°. They will not. Rewriting geometry.py repeatedly within the same second, with the same file length, let Python reuse a stale .pyc — so every run in that sweep was quietly re-measuring 70°. Re-run with -B and a fresh interpreter, the limit is 60.

Phases grouped, board A captured. The three phase cells are adjacent now, 0–210°, with the three utility wedges together on the other side: the RP2350A sits in the middle wedge instead of between two half-bridges, the motor leads leave as one bundle, and the heatsink land grew to 286 mm². The six M2.5 moved onto the section boundaries to do it, which costs the even 60° spacing and is worth it.

Then the schematic: 115 components, 81 nets, ERC clean, generated from a netlist in tools/schematic.py and cross-checked against the placement both ways. Capture found seven things — no core-buck inductor for the RP2350A, a bus divider that would have put 5.5 V on a 3.3 V ADC pin (and a 0603 asked to hold off 60 V), a floating FAULT_n, a USB_VBUS_DET with nowhere to go, a signal link whose pins had never been counted, three phase TVS that were in the parts table and not on the board, and a MOSFET whose symbol and footprint numbered their pins differently. Reading the INA241 datasheet moved the shunt again: the 50 V/V grade is A3, not A2, and the output only swings to V_S−0.2 V worst case.

Three more KiCad file-format facts, all found by the netlist diff rather than by ERC: a schematic's lib_symbols names units by the bare symbol name and gets them wrong silently; a sheet has two different uuids and the instance path uses only one of them; and two label stubs on one coordinate weld two nets together.

Board A placed, and 20 A RMS made real. 98 parts, DRC- and ERC-clean, from a new tools/placement.py that holds the floorplan and the rules it has to obey. Committing to 20 A RMS continuous rather than 20 A of full-scale sense turned up two errors in draft 0.2: the sense chain clipped at 14.6 A RMS, and the 2×8 power link had 0.8 A of margin against 23.2 A RMS. Both fixed — 1.0 mΩ shunts at 50 mV/A, two 2×5 headers. The EG2103 datasheet was read: LIN is pulled up, its truth table matches §6, and one sentence of its own prose contradicts the rest of the document. Six 4.7 k pulls went on anyway, because RP2350's reset-state pull-down against that 200 k pull-up parks the input at ~1.2 V — between V_IL and V_IH. Reading the sister project's actual board rather than its driver's datasheet also showed that draft 0.2's criticism of their F-17 was wrong: their E-stop brakes, because of four 10 k pull-downs.

Four KiCad file-format facts cost most of the debugging, and all four are now in the generator: pads carry an absolute angle (without it every fine-pitch part's copper is turned the wrong way, which DRC showed as a 1.27 mm-pitch SOIC-8 with 0.0000 mm between pins at 90° and nothing at 45°); custom pads need it separately; net classes want microvia_* and a priority or they are discarded silently; and the stackup did not add up to 1.6 mm.

KiCad projects started. tools/gen_boards.py emits both boards from tools/geometry.py: outlines, mount patterns, stackups, design rules, net classes and a hierarchical sheet skeleton. Both DRC-clean and ERC-clean, verified with kicad-cli — which caught two real format errors (justify center is not valid KiCad, and hand-rolled mounting holes trip lib_footprint_mismatch; the stock footprints are embedded instead).

Draft 0.2. Gate driver settled against real LCSC stock rather than a parts search: EG2131 and FD2103S are both out of stock, and EG2103 (C480654, 2,225, $0.19) is the pick — keeping EG Micro's logic convention, the interlock and a 560 ns hardware dead time, at about 2 W of switching loss against a 4 A driver. USB-PD restored as a first-class power source: a 20 V contract feeds VMOT, so the sister project's F-27 and F-39 come across as adopted fixes rather than avoided problems. Reading the EG3113 datasheet to settle the driver's float behaviour turned up a likely error in their F-17: it claims the E-stop brakes, and the part coasts.

Specification draft 0.1. Read the sister project end to end; pulled the MT6701 circuit and mount pattern from hardware/encoder, the power-stage numbers from review/gan.html §7 and review/power.html, and the inheritance list from review/findings.html. Diameter, power class, sensing and I/O settled. Geometry moved into tools/geometry.py so the drawings and the prose cannot drift.

Project created and registered with the hub. Status page scaffolded.