Specification

1 · What it is

Two identical-diameter round boards stacked on the back of a motor.

The split is drawn where it costs least. Everything with a fast di/dt loop — gate loops and commutation loops both — stays on board A. What crosses the interconnect is a DC bus, three regulated rails and a handful of slow signals.

2 · Mechanical

Area is not the constraint. The sister board fits a four-bridge stage, a twelve-pin switched encoder port, isolated CAN and USB-PD into roughly 4400 mm² of courtyard across two sides. This design has four usable sides of 2313 mm² and far less to put on them. That buys the right to keep thermally generous packages instead of chasing the shrinks in the sister project's F-47 — take the small parts where they are also better parts, not merely smaller ones.

3 · Power stage

4 · Thermal — what 20 A costs

Board A is a sealed sandwich: its inner face looks at the motor, its outer face looks at board B. Neither sees moving air. Everything else in this spec is comfortable; this is not, and committing to 20 A RMS continuous is a decision about the enclosure as much as about the board.

The switching row is where the driver choice lands. EG2103 sources 0.3 A and sinks 0.6 A, so against a 19.5 nC Q_gd the edges are 65 ns on and 32 ns off and no gate resistor below about 28 Ω changes that. Add the complementary body diode's 188 nC of reverse recovery at 60 V and the three bridges come to 3.84 W. A 4 A driver would save roughly 2 W across the board; that 2 W is the price of the hardware interlock and the 560 ns dead time, and it is a deliberate purchase.

The path out, in four resistances

So §4 of draft 0.2 asked which of four options to take, and the answer is option 2, taken seriously. The machined aluminium ring is not an optional upgrade that buys headroom — it is a structural member of the thermal design, and the board is now laid out around it:

• Every part on the outward face stops at R 29.2, leaving an uninterrupted annulus for the ring to clamp.
• Each phase cell offers a 58° arc of mask-free copper at R 29.2–31.5, between that cell's two perimeter bolts. With the six Ø4.8 mm bosses that is 286 mm² of metal-to-metal joint.
• The six M2.5 holes are plated, with pads on every layer and mask open both sides. They are the standoff, the heat path and the chassis ground bond at once.
• The motor leads land on the motor-facing face, so the ring needs no notches and the outward perimeter is entirely thermal.

Options 3 and 4 from draft 0.2 stay declined for the reasons given there: the motor housing is the hotter body in the case this drive exists for, and a finned lid on board B is on the wrong side of an 11 mm air gap. The ring is the only path that leaves board A's copper through metal.

5 · Sensing

The RP2350A has four ADC inputs, on GPIO26–29. That is the whole analog budget, and it is spent as follows.

Phase C current is reconstructed as Ic = -(Ia + Ib). What that costs is worth stating plainly: no per-phase fault detection, no redundancy, and any offset error in A and B lands doubled on C. For FOC on a wye-connected motor it is standard and sufficient.

A second NTC footprint sits by the motor mount pattern, DNP, with a 0 Ω jumper selecting which thermistor reaches ADC3 — so motor-housing temperature is a build option rather than a respin.

6 · Control — RP2350A

Thirty GPIO, of which this design uses twenty-one. QSPI flash, USB, SWD and the crystal all sit on dedicated pins and cost nothing from that budget.

Two details in that table are doing real work.

Each half-bridge sits on one PWM slice, and both its inputs carry the same waveform. GPIO 8/9, 10/11 and 12/13 are the A and B channels of slices 4, 5 and 6. Because EG2103's LIN is active-low, the driver does the inversion internally: its truth table has HIN = LIN = 0 turning the low side on and HIN = LIN = 1 turning the high side on. So PWM_CH_CSR.B_INV stays clear and both channels run the same duty. Dead time comes from the driver's own 560 ns, not from offsetting the compare values — and §3 now has the datasheet's truth table confirming that reading. Two consequences for the loop: the driver adds 780 ns of turn-on delay against 220 ns of turn-off, which is the dead time rather than a circuit alongside it; and an input pulse shorter than about 560 ns produces no output, so at 20 kHz the bottom and top 1.1% of the duty range are unreachable.

The status LED is three GPIO, not a WS2812. The sister project's F-16 is a WS2812B needing V_IH = 3.5 V from a 3.3 V GPIO, fixed by dropping the LED supply through a Schottky. With spare GPIO and no 5 V rail on board A, a plain RGB LED is smaller, cheaper and has no failure mode.

7 · Board B — power and I/O

Power tree

SOURCES ──────────────────────────────────────────────────────────────────

  XT30, 12–60 V ──────────────────────────────────────────→ VMOT
                  straight through, so regen can reach the pack

  USB-C VBUS ─┬─ FUSB302BMPX ── I²C ── CPU      PD sink, ≤ 20 V / 5 A
              │
              ├─ LTC4359 + E100N4P0HL1 ────────────────────→ VMOT
              │     ideal diode; blocks VMOT from the USB host.
              │     PD powers the drive instead of a pack, not with one
              │
              └─ Schottky ──────────────────────────────→ 5 V Vlogic
                    pre-contract path: logic only, no gate rail


RAILS ────────────────────────────────────────────────────────────────────

  VMOT ─┬─ SMDJ64A TVS  +  3 × 100 µF / 100 V bulk
        │
        ├─ the three half-bridges, board A
        │
        ├─ LMR38010 ──→ 12 V  Vgate   0.1 A    EG2103 × 3, board A
        │     EN pulled up: on unless GATE_EN pulls it down
        │
        └─ LMR38010 ──→  5 V  Vlogic  0.5 A ──→ SPX3819 ──→ 3.3 V
                                                  RP2350A + MT6701, board A

Two independent bucks off VMOT rather than a cascade. Same part twice, and a fault in the gate rail does not take the CPU down with it. Both are LMR38010 (4.2–80 V, 1 A synchronous), F-47's recommended replacement for the sister board's XL7005A. The 12 V rail is enabled by GATE_EN from the CPU — on by default, with a pull-up the CPU can override, because a reset is meant to brake and a brake needs the gate rail (§3). Both regulate happily from a 20 V VMOT as well as a 60 V one, which is what makes the next section work.

VMOT runs down to 12 V (decided 2026-09-22), and that is the one place the gate rail does not regulate: the LMR38010's maximum duty cycle is 97%, so at a 12 V bus the 12 V rail sits in dropout near 11.5 V. That is still above EG2103's 9.7 V V_CC turn-on, the bootstrap reaches about 10.6 V against the 9.6 V V_B turn-on, and the FETs see about 11 V of gate against the 10 V their R_DS(on) is specified at. Below 12 V none of that holds, which is why 12 V is the floor rather than a nominal.

Full-duplex RS-485, two ports

Four-wire RS-485, so the master can transmit whenever it likes and only the drives need to arbitrate. Two connectors wired pin-for-pin in parallel: the cable runs in one and out the other, and the bus is a bus, not a repeater chain. No firmware is in the path of a pass-through, so an unpowered or crashed drive does not break the run below it.

Naming the pairs by direction rather than by A/B is deliberate: a straight cable then wires itself correctly, and there is no crossover to get wrong at 3 a.m.

Two SIT3088ETK (DFN-8, already sourced by the sister project) rather than one full-duplex part: one strapped permanently as a receiver on the DOWN pair, one as a driver with DE on the UP pair. Cheaper than a MAX3491, in a package that is already in the library, and it puts the failure modes somewhere already understood.

USB-C

Full USB-PD sink, as on the sister board: FUSB302BMPX negotiating over I²C from the CPU, up to a 20 V / 5 A contract. The sister project's two highest-severity power findings are both PD front-end bugs, and both have adopted fixes that come across as fixes rather than as problems to rediscover:

• F-27 — the backfeed blocker. Their LM74700 is a 65 V part with its cathode sitting on a 60 V VMOT: five volts of margin against a rail that regen actively pumps upward, and a failure mode that connects the motor bus to a laptop. Adopted fix, taken here verbatim: LTC4359CMS8 (4–80 V operating, 100 V abs-max pins) driving an E100N4P0HL1 (100 V, 4 mΩ, PDFN5×6), which also keeps the 5 A path under 0.1 W where a Schottky would burn 2.75 W.
• F-39 — the ESD part. USBLC6-2P6 references its steering diodes to pin 5, which has an internal ~6 V zener; on VBUS that survives 5 V and dies the first time a 20 V contract is agreed. Pin 5 goes to +3V3, and VBUS gets its own clamp at the connector, sized against FUSB302's ~28 V VBUS absolute maximum.

The 20 V capability is the reason to be careful here rather than a reason to drop PD: it is also what makes the drive useful on a desk with nothing but a laptop charger.

8 · Interconnect

Two connectors, so the 60 V bus never runs beside USB or SWD. The signal count is set mostly by keeping PD on board B: the FUSB302 sits next to the USB-C connector where the CC lines are short, but the CPU that negotiates with it is on board A, so its I²C and interrupt cross the interconnect.

The six perimeter screws do the alignment and carry the mechanical load; the connectors only have to mate. Their mated height and the standoff length are the same dimension and must be ordered as one decision. Note that the screws are now plated and grounded on both boards for §4's sake, which puts six brass standoffs in parallel with the header's ten ground pins — free return path, and a reason the link is less stressed than the arithmetic above assumes.

An alternative worth pricing before committing: make two of the six perimeter standoffs the power path — brass, into generous plated pads on both boards — and drop the header entirely. It is mechanically cleaner and electrically excellent if the joint is sound, and the whole question is whether a screwed joint's contact resistance is trustworthy over thermal cycling. Not the kind of thing to adopt without a bench test — and it now collides with §4, which wants all six of those screws carrying heat and ground, not two of them carrying 60 V.

9 · What this inherits, and what it fixes

The sister project's findings register is the most valuable thing it hands over. These are the rows that apply to a board that has not been built yet.

Three things are worth handing back. The first is a correction to draft 0.2 of this document rather than to their register.

RP2350 erratum E9 reaches the gate driver, and that is the second. A Bank 0 GPIO can latch around 2.1–2.2 V, and at reset the pin is an input with a pull-down; against EG Micro's internal 200 k pull-up on LIN the divider lands near 1.2 V, between V_IL and V_IH. Their four pull-downs happen to defeat both at once. Anyone copying the circuit without them — as draft 0.2 of this spec proposed to — puts a gate driver input in the undefined band. The answer is an external pull in whichever direction you want, sized ≤ 9 k, and stated in the schematic.

F-40 needs a replacement driver regardless. EG2103 is the cheap like-for-like, but for their four-bridge board NCP5183DR2G is probably the better answer: 600 V, 4.3 A both ways against EG3113's 2/2.5 A, matched 120 ns propagation delays where EG3113's are asymmetric — their own F-41 notes its working margin comes mostly from that asymmetry — plus 50 V/ns dV/dt immunity, AEC-Q100, $0.92, MOQ 1, 2,883 in stock. It gives up the interlock and the internal dead time, which their GaN evaluation already argues they do not lean on. This board took EG2103 instead precisely because it is not thermally tighter than they are and can afford to keep the interlock.

F-41's remedy, a 12 V rail, is the last — harder there than here, because thirteen TS5A3159 analog switches sit on their 5 V rail at 5.5 V max. Worth noting it only buys about half the gap on its own: with EG3113's 2/2.5 A the resistor still sets the edge, so the rail and the resistor sweep in F-41 are complementary, not alternatives.

10 · Layout and capture — board A

Board A is placed, captured and routed: 136 parts, 87 nets, 425 pin connections, 78 on the outward face and 58 on the motor-facing face, ten DNP. Every connection is made; DRC finds nothing, ERC finds nothing, and KiCad's own exported netlist matches the one this repo intended — net by net, connection by connection. §10b is the routing.

The schematic is generated from a netlist in Python, not drawn: a component is a reference, a symbol, a value, a footprint and a pin-to-net map, and tools/schematic.py emits four hierarchical sheets from that. The sheets are drawn with labels rather than wires — every pin gets a 2.54 mm stub and its net's name. That is an honest description of what it is: routing wires between 115 parts automatically produces something worse to read than a table. What it buys is that the designators, the footprints and the DNP flags are one source of truth, checked in both directions on every build. gen_boards.py will not write a board if a part is on it and not in the netlist, or in the netlist and not on it, or if their footprints disagree, or if any symbol pin has no net.

The phase cell

All three are identical, at 60°/180°/300°, so all three commutation loops are the same shape. Radially outward from the centre keepout:

On the motor-facing face: the amplifier at the cell's centre with its SNSP tap and its filter cap clockwise of it within 0.4 mm of R 18.4, arranged for two arcs rather than for a router; the gate bleeds directly beneath the gate resistors, one via through both pads; the two shunts side by side under the switch-node island between the FETs' via clusters, their SW pads over the switch-node pour and their PHASE pads in the phase-output pour, because nowhere else on the back is clear of the DC-link caps' vias coming through; the arc lead pad at R 28.5–31.3; and the channel at R 29.3, holding the clamp diode.

How it is kept legal

tools/placement.py holds the floorplan and the rules it has to obey, and gen_boards.py refuses to write a board if any of them fail. Parts pack into rows at a radius; a row proposes a position and then walks it outward until the courtyards genuinely clear, because two rectangles 0.3 mm apart along an arc are also rotated relative to each other and can still have corners inside one another. On top of that it checks: nothing past R 31.5 or inside R 16, nothing outside its own 60° sector, nothing touching a perimeter boss pad, nothing on either arc, and — the one a same-side courtyard check cannot see — no through-hole pad landing on a part on the other face. That last rule is what found the FET thermal vias sitting on the shunts.

Three footprints are generated rather than drawn, from the same constants as everything else: the PowerPAK SO-8 with its sixteen-via drain array, the M2.5 thermal boss, and the two arc pads. Change FET_VIA_PITCH or the land radii in geometry.py and the footprints follow.

10b · Routing — board A

Most of this board is not routed and was never going to be. Ground is two solid inner planes; VBUS is a sector of a third and +3V3 is the rest of that layer — the CPU wedge and the whole centre disc; each switch node and phase output is a pour on F.Cu and B.Cu, because 20 A does not go down a track and §4's IPC-2152 figure is about 6 mm of 2 oz copper. What is left is the signals, and those go to freerouting — less the ones it turned out to do badly, which are made first, as copper, and taken away from it.

Where it got to: 1361 track segments, 278 vias, and every one of the 425 pin connections made. DRC finds nothing, ERC finds nothing, KiCad's own exported netlist matches the intended one net for net. 212 of the vias are the tools' — 112 stitched into pads, the rest the fan-out's — and freerouting made the other 66. No foreign copper under the heatsink land, every annular ring legal, no right-angle corners. That is the 2026-09-22 board; the one before it was 1351 segments and 283 vias, and this one routed in freerouting's first round as that one did.

The maze

The last few connections are not hard because the board is full. They are hard because they are last: the lanes out of the QFN's via field go to whichever nets reach them first, and what is left over cannot be routed by anything unwilling to move what is already there.

tools/finish.py rasterises the board — one bitmap per routable layer (F.Cu, In3, B.Cu; In1 and In4 are ground and In2 the power planes) at 0.05 mm, every foreign shape drawn and then grown by the clearance it wants, 0.15 mm or 0.4 for the 60 V nets, by a distance transform. Then A* from one piece of the net to the other, eight-connected so every step is 45°, with a via as a move between layers wherever a via fits; and the chain of cells that comes back is folded into as few segments as the free space allows. The grid proposes and the exact clearance test disposes: what it rejects is punched out and the route planned again.

Two things the maze must know that KiCad's clearance rules do not cover, both found by DRC after the first run. The board edge — the clearance test is copper against copper and the outline is neither, so the simplifier cut a corner 0.4 mm outside the board. A bare drill — an M3 mounting hole is NPTH, it has no copper, and min_hole_clearance is the only rule that mentions it; seven tracks ran within 0.16 mm of the four mounting holes before the grid was told about drills.

Why the fan-out is a tool and not a pass

A 0.4 mm-pitch QFN cannot take a via per pin in place: 0.2 mm pads, 0.2 mm between them, a 0.46 mm via wanting 0.15 mm around it. Every via row in front of the chip takes lane width from the stubs that still have to pass it. With 0.15 mm stubs, a row of vias every fourth pin leaves 0.84 mm between two of them and the three stubs passing through need 0.75 — 0.09 mm of margin, which is why the fan-out is four rows deep. The stubs are threaded rather than bent: a stub steps 0.06 mm aside for the length of a neighbour's via and comes back, because held aside for a whole row interval two neighbours passing vias on opposite sides met in the middle 0.03 mm too close. It is a small dynamic programme over (waypoint, lateral offset) and finds 51 of 52 vias in five seconds.

What the Specctra round trip got to decide

All of it measured on the way back, not read about:

1. Freerouting does not treat a Specctra plane as connecting anything — nor as an obstacle. Ground is taken off the table before export: the planes go, the net goes, In1/In4 are declared power layers. And every 20 A pour is a keepout by the time the router sees it, because given as a plane it lays a foreign track straight through and KiCad cuts the pour around it.
2. A protected via is protected on its pad's layer, by the pad, and nowhere else. The ground vias are removed from the DSN and each leaves a keepout on all four signal layers.
3. KiCad's SES import takes a via's diameter from the Specctra padstack and its drill from the netclass. A 0.46/0.20 stitching via came back 0.46/0.40, a 0.03 mm annular ring; every drill is rebuilt from the diameter on the way in.
4. Specctra has no hole-to-hole rule. via_via and via_pin clearance stand in, and a class with a rule of its own does not inherit them from the structure rule — measured as two Analog-class vias 0.48 mm hole to hole — so every class rule carries both.
5. The router routes to the boundary it is given; the outline is pre-inset by 0.35 mm, exact because it is a circle about the shaft axis.
6. PAD::GetLayer() answers F.Cu for a pad on a flipped footprint. Only the layer set knows.
7. KiCad's DRC report names items by uuid, and a footprint embedded verbatim carries the library's pad uuids, so six FETs shared them and the unconnected list named the wrong gate for three runs. Every embedded item has a uuid of its own now.

What freerouting turned out to do

Measured, mostly from its log and some from its bytecode, after four runs in a row stopped at the same thirty connections:

1. A wire touches a pad only if it ends on the pad's centre, exactly. Freerouting computes that centre itself from the placement rotation, rounded to 0.1 µm; KiCad writes wire ends to the micron. A stub starting on its pad's centre was a separate island to the router, which then queued 119 connections between pads and their own stubs and could insert none of them. route.py rewrites every wire end within 30 µm of a pin or via of its net onto the centre the router will compute.
2. In 45-degree mode it cannot leave a pad that is not on the grid. Its search tree wraps a tilted pad in its bounding octagon; for the FET gate pads that runs into the halos beside them ("no accessible expansion doors", every gate, every pass), for the flash and the amplifiers it overlaps the neighbours. Free-angle mode routes them and takes twenty-five minutes a pass where 45-degree takes five seconds. So those pads get copper from the tools.
3. A protected wire is a bad target. A junction into a protected trace cannot be inserted (791 times in one run), and a three-segment protected polyline joined twice loops normalization for ever. So the router is not shown the stubs: a pin with its stub and via leaves the net's pin list, the stub becomes a keepout, and the net's end is the via — a circle, on the grid at any angle. Passes went from thirty-five seconds to five.
4. Its last pass can undo its earlier ones: a failed attempt does not put the neighbours it ripped up back, and the session comes back with nets that have their vias and no wire. route.py runs rounds, each exporting the board as it stands.
5. A locked track exports as (type fix) and an unlocked one as (type route) — the only handle on my copper versus the router's across the round trip. A strict round protects both; the rounds after the first are loose, protecting only the tools' copper so the router's own earlier wires are its to move. It does not rescue the last few nets — told it may move them, freerouting reports "board state has not changed since pass #1" and stops — but it makes the rounds safe to repeat. KiCad's session import keeps a locked item and the session carries its own copy of some protected vias, moved up to 25 µm, so the copy goes and the original stays.
6. A class naming a net that no longer exists makes freerouting read nothing and write an empty session, silently. -inc does nothing in 2.2.4 headless.

45 degrees, and no stair steps

The tracks that come back are measured, not assumed: every segment is bucketed by direction and every corner where a horizontal segment meets a vertical one is counted and then chamfered — both new endpoints lie on the old track and the diagonal lies inside the corner it replaces, so a chamfer only ever removes copper. What is on the board: 360 segments at 45°, 361 orthogonal, 640 at neither, the last being the tools' — pad exits along a rotated pad's axis, the gate and sense arcs, and a fan-out radial to a chip at 270° on a board where nothing is on the grid. No right-angle corners, and 8 tees, which are junctions rather than stair steps.

Four repairs run after the round trip, all deterministic. Degenerate segments: Specctra leaves sub-micron stubs that turn a 45° bend into a right angle with nothing to cut. Hole-to-hole: a few drills come back 20–40 µm too close; a narrower drill moves no geometry, and where that is not enough the via is nudged. Unused vias: an escape the router did not use is copper on one layer, and KiCad is the judge of that — the via goes, then its stub. Pour islands: routing cuts the ground pours into pieces, and any piece without a via of its own gets one.

One more check runs on the way out, and it is not a DRC rule: no foreign copper on F.Cu where the heatsink ring clamps, R 29.2–31.5. That contact is the 20 A rating of §4, the ring is aluminium, and anything but ground under it is a short waiting for the screws.

11 · Open questions

1. Which motor? Everything mechanical is provisional until this is answered: the encoder air gap, the standoff length, whether the 25 × 19 mm pattern actually bolts to something, and whether the rear face is stationary. Needed: the motor, its rear bolt pattern, and how the magnet is carried on the shaft.
2. Thermal path — decided: option 2 on the board, and no rating beyond what the prototype shows. The board is laid out for a machined aluminium ring between the boards, clamping the bare copper and bolted through all six perimeter holes. Its outside was question 13, and 2026-09-22 answered it: no fins. The drive runs well below its peak current in normal use, and 20 A RMS is a burst to be measured on the prototype, not a continuous rating (§4).
3. EG2103's LIN pull direction — settled from the datasheet: it is a pull-up, and a floating input coasts. Truth table, block diagram and the sign of I_in(L) all agree; only one sentence of the PDF's own prose disagrees, and it contradicts itself in the same breath. See §3. The pull resistors got fitted anyway, for the unrelated reason that RP2350's reset-state pull-down parks LIN in the undefined band — and since question 8 was answered they pull LIN down, so the board brakes.
4. The channel can only hold ground and phase-output parts — decided: the cells were widened to 68° and five parts per cell came back in. Inside a phase cell the channel row on B.Cu is boxed in three ways: the phase-output pour owns B.Cu from R 25.9 to 28.9 across ±11.5 mm, so a channel part's inner pad at R 28.5 sits inside it and cannot trace inward; the heatsink land owns F.Cu from R 29.2 out, and that is bare copper under an aluminium ring, so a foreign-net via there is a short rather than a DRC error; and the six boss pads cut the outer B.Cu ring into six disconnected arcs. What is left is a via corridor about 0.7 mm wide, twice per cell. Neither pour can give the room back — the phase band is already 95 A/mm² at 3.0 mm wide and cannot grow inward past R 25.6 without meeting the switch-node band.

   So C{n}03/C{n}04 went into the DC-link row ahead of the bulk, where a high-frequency capacitor belongs; D{n}01 went beside the bootstrap capacitor it charges; R{n}11/R{n}12 went onto the driver's logic side with the VCC 100 n. D{n}02 stayed, because its nets are exactly GND and the phase output.

   67° is the floor — below it the DC-link row runs into the perimeter boss and the wedges lose their corners — and 68° is set, for a degree of margin. The cost is the even bolt circle, which is what the 60° arrangement was pleasing for; bolts are now at 0/68/136/204/256/308°. Against that, the heatsink land is measured from the cell edge, so it grows from 250 to 279 mm².

5. Bus input connector — decided 2026-09-22: XT30, as on the sister board. Whether power also chains was not part of the answer, so board B gets one XT30 and no power out; an in/out pair beside the RS-485 ports is still possible, at the cost of board-B perimeter and a real fault-current question.
6. Does VMOT ever run below 20 V? — decided 2026-09-22: yes, down to 12 V. Two consequences, both in §7. The gate rail runs in dropout at the bottom of the range, near 11.5 V, which EG2103 and the FETs accept and nothing lower would. And a 20 V PD contract could now back-drive a lower-voltage pack — answered the same day by not using the two together: PD replaces a pack. The XT30 stays a straight pass-through.
7. E-stop. Keep the sister board's expandable loop pulling RUN, now that it actually works? It costs a two-pin connector and it is the only thing that stops a wedged CPU. My inclination is yes.
8. Brake and regen. What a reset does is decided (2026-09-22): it brakes. LIN and HIN are both pulled to GND, the low sides conduct whenever the CPU is not driving, as on the sister board (§9), and board B holds the gate rail on through a reset so that the brake lasts (§3, §7). Regen is still open. A decelerating load pumps VMOT into the bulk and then into the TVS — the simulation has the bus at the TVS in 0.26 ms at the design-point braking torque, with about 2 J for a part that survives a few — and there is no brake resistor and no active clamp. A brake resistor, an active clamp, much more bulk, or a documented deceleration limit. A pack on the XT30 absorbs some of it, which is why the XT30 has no ideal diode; on USB-PD nothing does, because the PD path's diode blocks it.
9. Hardware overcurrent. A comparator on the INA241 outputs pulling RUN is about four parts and closes the loop faster than firmware can. Populate, DNP, or leave out? Capture forced half an answer: FAULT_n now has a 10 k pull-up, so the not-fitted state is defined rather than floating. The comparator itself is still a question.
10. Interconnect: header or standoff? §8. Wants a bench test, not an opinion — and it now competes with §4, which wants all six perimeter screws carrying heat and ground rather than two of them carrying 60 V.
11. Firmware — decided 2026-09-22: SimpleFOC, as on the sister board, whose firmware, tuning scripts and dashboard all transfer. Its shunt scaling does not transfer: 50 mV/A here, 100 in the precision mode, against its 80. Three changes from the simulation are waiting for it: pace the ADC from the PWM slice's wrap (one conversion per phase at the counter's zero), set dead_zone to zero and leave the dead time to EG2103, and never command a duty the driver's 560 ns minimum pulse cannot reach.
12. Board B is not captured. Board A is done; board B is still an outline and five empty sheets. Two things are waiting there and both came out of board A's arithmetic: its bulk needs sizing for ~9 A RMS of ripple rather than for capacitance (§8), and the RS-485 fail-safe bias has to be computed against the termination rather than guessed (§7, their F-01).
13. How big are the fins? — decided 2026-09-22: there are none. §4 had made the enclosure the 20 A rating; the answer is to stop asking for that rating. The drive runs well below its peak current in normal use, and what it can do in bursts will be measured on the prototype. Whether connectors may overhang Ø65 is still open, with the enclosure.