servodrive — electromagnetic simulation

Summary

What the simulation found

Q1

The commutation loop is five times the estimate

The board was designed on geometry.commutation_loop(), which models the loop as a 15.4 × 5 mm strip 0.1 mm above the In1 ground plane and gets 0.387 nH for the PCB part. The board does not do that. VBUS has exactly one zone, on In2, and no tracks: the high-side drain reaches it only through a 4 × 4 field of 0.4 mm barrels whose antipads perforate In1, and the DC-link capacitors reach it through one via each. The loop's outward leg therefore runs 0.55 mm below F.Cu with a ground plane in between.

Solved on the copper as routed, with both devices shorted at their own pads so the number is the PCB's alone, the loop each capacitor sees is 2.52–2.84 nH, and with all four in parallel — which is how they work, strongly coupled — 2.06 nH, 5.3× the estimate.

Adding the two packages (1 nH, bracketed — Infineon does not specify the SuperSO8's lead inductance) and the capacitors' own ESL gives a total of 3.19–3.35 nH against the 1.99 nH the design assumed. The overshoot that line of the table quotes is still the design's own arithmetic — L times the 0.87 A/ns it assumes — and it is wrong for a second reason: the transient in Q2 commutates at about five amps per nanosecond, not one. The peak the circuit actually reaches is in Q2, not here.

Cells B and C

the three cells differ by 15.2 %, so the neighbourhood does matter and cell A is not representative. Cell C is the one whose neighbour is the power-link wedge, where VBUS and GND enter the board, and it is the one that differs.

Mesh convergence

The grid this was solved on is not fine enough to be the answer: a filament grid that coarse cannot let the return current concentrate under a leg running 0.4 mm above it, and that concentration is most of what sets this loop. Refined, it runs from 2.35 nH at 1.8 mm to 1.98 nH at 0.75 mm, the last refinement moving it 1.6 % and in the other direction — so it has settled, and the converged figure is 1.98 nH against the 2.06 nH this report quotes elsewhere, 4 % lower. Q11 drives the same single port in a full-wave solver and, with its own device strip de-embedded, gets 2.91 nH against this model's 2.68 nH for that port — 9 % apart. Everything the number is used for — that the loop is several times the 0.39 nH the board was designed on — holds across all of it.

Skin effect

The sweep uses one filament through the 35 µm copper, which is exact below about 1 MHz and does not push current to the surface above it. The same model with three filaments, at 20 MHz, gives 1.8× the loop resistance and 0.983× the inductance: the resistance in the sweep is a lower bound above a megahertz, the inductance is not affected.

Q2 / Q3

Overshoot meets the criterion at the driver impedance the datasheet implies, and misses it at a strong output stage

Both edges were simulated, with the FET fitted to its own datasheet (see the method section) and the loop parasitics from Q1. The design expected 61.7 V of peak V_ds. The answer is not one number, because it is not set by anything on this board: it is set by how hard the EG2103's output stage actually drives, and the only EG2103 document that could be obtained gives I_O+/I_O− without the condition they are measured at.

Read those ratings the usual way — as an output resistance at the 12 V drive, so 40 Ω sourcing and 20 Ω sinking — and the worst V_ds anywhere in the operating envelope is 62.6 V, against a 68 V criterion, a 71.1 V TVS and 80 V of silicon. Give the same part a strong output stage instead (4/2 Ω) and it becomes 73.9 V.

The bracket that decides it

R_g and junction temperature, at the datasheet reading

Neither moves it. At this output impedance the gate resistor is a tenth of the path that charges the gate, so changing it from 2.2 to 22 Ω changes the edge by a few per cent, and the turn-off overshoot only falls from 62.6 to 61.9 V. The junction temperature does not appear at all: it changes R_DS(on) and the body diode, neither of which sets this edge.

There is no ring to fit at the datasheet reading. The turn-off edge leaves 2.6 V above the rail and comes back without completing three half-cycles about it, and the turn-on approaches the rail from below with a decaying oscillation that never crosses it; either way Q2's five-cycle decay criterion is met. With the strong output stage the turn-on does ring, at 145 MHz for 31 cycles, which is the one criterion that corner fails on top of the peak. The frequency is close to the 100 MHz the design estimated from 1/(2π√(L·C_oss)); the loop is bigger and the capacitance smaller than assumed, and the two partly cancel.

Sensitivity to the device's capacitance

Against the datasheet's own switching test the fitted model is faster on 3 of its 4 times at the typical capacitances, by up to 42 % (t_d_off 25.1 vs 43 ns). At the maximum capacitances every one of them is slower than at the typical, and they straddle the datasheet's figures rather than sitting on one side of them, so the two corners bracket the edge rate rather than pointing at one. Every edge-rate-sensitive answer is run at both.

Q3 — the snubber

The smallest one that meets both criteria is 2.2 Ω with 0.47 nF, which brings the worst V_ds to 62.7 V and costs 0.034 W per cell at 20 kHz. The loss is C·V²·f and does not depend on R; R only sets the damping. At the driver impedance the datasheet implies, nothing needs snubbing — this is the part to fit only if the output stage turns out to be the strong one.

Q4

The off device sits above its own minimum threshold on every edge, and it is charge, not layout, that puts it there

The question is whether the device that is off gets turned on by the other one's edge. The criterion is an induced V_gs below 0.7 × the minimum threshold, 1.54 V, at 1.2 kV/µs and at twice that.

The switch node does not slew at 1.2 kV/µs. Depending on the driver's output impedance — the open question of Q2 — it slews at 6 to 52 kV/µs, because the fast part of the turn-on is not the gate charging C_gd; it is the low-side body diode snapping off and its recovery current dumping into C_oss. Across every combination of R_g, drive strength, capacitance corner and driver impedance, the induced V_gs at the die stays between 2.44 and 3.62 V — above the 1.54 V criterion and above the 2.2 V minimum threshold itself, and almost independent of everything in the sweep.

The gate loops, solved

Both loops are heavily damped — the gate resistor, the driver's own output impedance and the device's 1.6 Ω see to that — so the gate does not ring, and the loop inductance is not what sets the answer below. The answer is set by charge.

Two voltages are reported because they are different things. The channel responds to the polysilicon gate against the source; a probe on the board sees the package pin, which the Miller current's own I·R drop across that 1.6 Ω lifts a further 6.7 V at the fastest edge. The die number is the one the criterion is about.

Whether it actually conducts

The criterion is a voltage, but what matters is whether charge goes through the channel of the device that is supposed to be off. So the same edge was run twice more: once with the low-side device at the bottom of the datasheet's V_GS(th) distribution, and once with a device whose threshold is out of reach but whose capacitances and charges are identical. The difference between the two is cross-conduction and nothing else — no displacement current, no recovery charge.

At the typical threshold there is none: -23 nC, which is the numerical floor of the difference. At the datasheet's minimum threshold there is 715 nC — 43 µJ of extra loss on that edge, and the high-side peak current rises from 56 to 74 A. At 20 kHz that is 0.86 W in one half-bridge if every turn-on does it, on top of the switching loss that is there anyway.

The usual fix does not work on this part

A capacitor across the gate and source pins is the standard answer, and it does almost nothing here: 22 nF moves the die from 3.62 to 2.52 V. The reason is the device's own 1.6 Ω of internal gate resistance: it sits between the pins and the polysilicon, so an external capacitor reaches the die through a 35 ns time constant while the edge it is supposed to absorb lasts a few nanoseconds. It is very effective at the pin — which is where a scope probe is, and why this fix is often believed to have worked.

Q5

The tap swings 7 times the signal, and the amplifier's hold is what saves it

Full scale across the shunt pair at 28.3 A is 22.6 mV. During an edge the voltage between the two tap points reaches 159 mV — 7 times the signal — which is hypothesis H3, and the solved partial inductances say where it comes from: the tap loop itself, not only the shunt element.

Solved on the copper: the current path from the low-side drain to the lead pad is 3.23 nH, and the transfer inductance between it and the two tap points is 0.0243 nH with 53 µΩ beside it. At the design's own 0.87 A/ns that is 21.1 mV — already the size of the signal — and the turn-off in Q2 commutates about five times faster than that. The shunt part's own ESL, bracketed at 0.2–0.5 nH because no part has been chosen, adds 8–19 times the signal on top.

H4 — the taps are not symmetric

The two taps differ by -0.064 pF to the switch node; a 60 V common-mode step therefore injects 3.9 pC of differential charge into the tap network, which the 1 nF across it turns into 3.869 mV -- against 22.6 mV of full-scale signal. The two taps' capacitance to the switch node is 0.009 and 0.074 pF: SNSN has about 8 times SNSP's, which is H4 in one number. The tiling is 158 panels, so this is the size of the effect rather than three figures of it.

What saves the measurement is the amplifier. The INA241A3 detects a large common-mode slew and holds its output for a microsecond (SBOSA30D §7.3.1.1). Inside that window the output is not wrong, it is stale — and since the phase current cannot change appreciably in a microsecond, stale is almost as good as right. The peak error the ADC could see is 27 LSB.

Q6

The sense chain is accurate; the copper costs 3.6 per cent

The taps are voltage probes, so this is a four-terminal measurement: the phase current is driven through each pour between the places it really enters and leaves, and the tap pads are read without drawing current. What the amplifier sees is the shunt plus whatever potential difference the copper puts between the two probe points.

Cells A and B meet both criteria. The copper's contribution is almost all on the PHASE side: R108's tap sits at the lead-pad end of the pour, so the measurement includes the whole run from the shunt to the lead.

The two 1.6 mΩ shunts share 51.7 / 48.3 %, an imbalance of 6.7 % against the 10 % criterion.

Q7

Twelve of sixteen vias under each low-side drain are islands

The consequence is that the phase current crossing from the F.Cu switch-node island to the B.Cu pour — which it must do, because the shunts are on B.Cu — goes through four vias and the two discrete ones nearby. The busiest carries 7.3 A at the 28.3 A peak, 5.16 A rms, against the 2 A rms a 0.4 mm barrel with 25 µm of plating is worth.

The high-side arrays, which are connected

Those sixteen do all reach In2, but they still share badly — the current crowds into the vias nearest where it comes from, and the spread is 139 % of the mean.

Grid convergence

The resistance converges; the peak current density does not, and cannot — it is a single cell at a re-entrant corner and grows without limit as the grid is refined. The percentiles are the numbers to compare with a width rule.

Q13

The link is fine; board B's bulk chemistry is not free

The DC-link current waveform was synthesised from the switching functions of three centre-aligned sine-PWM legs at m = 0.8 and 20 A rms, which gives 12.37 A rms of ripple — the same number geometry.interconnect() gets from its closed form, which is a useful agreement between two independent derivations. What differs is the split, because the impedances differ.

The bulk chemistry decides it. With four 100 µF polymer hybrids the bus ripple is under two volts; with the three 100 µF electrolytics the spec originally listed, at 0.2 Ω of ESR, it is over six. The link carries about 20 A rms either way, inside the 30 A ten pins are worth.

The link itself — twenty mated pins and six brass standoffs across an 11 mm gap — is 0.81 nH and 0.18 mΩ at 1 MHz; the standoffs take 12 % of it off the header.

Q10

The magnet is too strong at the short gap; the leads, not the copper, move the angle

The MT6701 wants 20–100 mT at its own surface, over an air gap the datasheet allows to be 0.5–2.0 mm. The board carries a Ø8 × 2.5 mm diametric magnet where the datasheet recommends Ø6.

At the nominal 1.5 mm gap the board's stack-up specifies, and at 1.0 mm, an N35 Ø8 magnet is inside the window. At the short end of the tolerance it is not, and an N42 is over the limit at 1 mm as well. The datasheet's own Ø6 gives 88 mT at 1 mm, comfortably inside.

The phase currents put 0.14 µT at the sensor from the board copper and 136 µT from the leads — a factor of 949. The board copper contributes little because the three phase pours are symmetric about the shaft axis and their in-plane fields cancel; the leads, which leave the board at three points and do not, are what is left.

The angle error that leaves is 0.09° peak, 4.1 LSB of the 14-bit word, against the 0.05° criterion. It is a gain-like error — it moves with the current — and what it costs is not torque, which loses 0.0001 % to the cosine and is nothing, but 0.045 A of misplaced d-axis current: real current, heating the windings and producing no torque.

Q8

Synchronised sampling is worth three times the noise

The firmware's ADC runs free, round-robin over four channels at 500 kS/s, so each current channel is refreshed every 8 µs and loopFOC() reads whatever the last conversion was. The question is what that costs against sampling once per PWM period at the counter's zero, where the ripple crosses its own average.

Measured against the average i_q over each PWM period — which is what the loop is trying to regulate — free-running sampling gives 0.638 A rms of error and 1.82 A of bias. PWM-synchronised sampling gives 0.21 A rms and 0.84 A: the noise falls by 3× and the bias by half.

The residual bias is not the sampling — it is the low-pass filter's group delay on a rotating frame, and it belongs to the control design rather than to the ADC.

Where the error lives

the current loop's own bandwidth is about 1 kHz, so error below that is what it will try to follow and error above it is what the low-pass takes out Most of the free-running error sits between one and five kilohertz — at and just above the loop's own bandwidth, which is the worst place for it to be, because the loop is fast enough to chase some of it and not fast enough to reject it. Synchronised sampling takes that band down by 3×.

Q9

The software dead zone buys nothing the hardware has not already taken

The EG2103 turns on 780 ns after its input and off 220 ns after it; the 560 ns difference is the interlock, and it is in the hardware whether the firmware asks for it or not. On top of that SimpleFOC's dead_zone = 0.02 takes another microsecond off each edge in software.

The software term costs 0.76 % of torque and leaves the distortion essentially unchanged: the hardware's 560 ns already dominates. Distortion is worst at low current, where the dead time is a large fraction of the conduction interval — which is the usual shape and the reason dead-time compensation exists.

The minimum pulse the driver will pass makes duties below 2.4 % unreachable, and by symmetry the same at the top of the range.

Q14

The bus guard is the only brake

There is no brake chopper: the sibling's fourth leg and 15 Ω resistor are not on this board, so a decel has nowhere to put its energy except board B's bulk and the two TVSs.

The bulk is worth a fraction of a joule between 60 V and the TVS's breakdown. A decel at the design-point braking torque drives the bus into the TVS in a fraction of a millisecond, and what is left over is tens to hundreds of joules — orders of magnitude past what an SMDJ64A survives.

Q11

Full wave: the loop cross-check and the far field

The commutation loop of Q1, on the same copper, in a solver that shares nothing with the first one: FastHenry is PEEC, quasi-static, no dielectric and no displacement current; openEMS is FDTD, the whole of Maxwell on a staircased grid. Driving the same port — the high-side C103 capacitor, the other three left open — openEMS gives 2.91 nH against FastHenry's 2.68 nH, 9 % apart. PASS against the spec's 25 % gate. The FDTD figure is the FDTD value with the device strip de-embedded; its raw value at the finest mesh is 3.04 nH, and FastHenry's is the converged end of its own grid sweep rather than the 1.2 mm production grid, which reads 2.72 nH.

What it takes to mesh this

There are no nets in an FDTD model, only metal: two conductors that come within one cell of each other are one conductor. The tightest net-to-net clearance in this window — barrel walls included, and it is the antipads the VBUS barrels pass through in the In1 ground plane — is 0.40 mm, so a mesh that does not stay well inside that joins VBUS to GND and the loop comes back far too small. A uniform mesh does exactly that: it reads 0.62 nH at 0.55 mm cells and does not reach 3.29 nH until 0.2 mm, by which point it costs more cells than the snapped mesh that gets there at 0.35 mm. The mesh used here is snapped to the copper instead: every polygon vertex and every barrel wall pins a line, so a clearance is resolved by construction rather than by where the grid happens to fall, and the fill between them stays coarse.

A uniform mesh, for comparison

Snapped to the copper

Each L here is the intercept of that fit, not a mean over the band: the band mean is 15 % higher because it includes the climb towards f₀. The residual is what says one L and one C describe the port at all.

And what it takes FastHenry

The two solvers approach this loop from opposite sides, and the mechanism is different at each end. A uniform FDTD mesh reads low until its cells are inside the board's 0.40 mm clearances -- there are no nets in FDTD, only metal, so a cell that spans a clearance joins VBUS to GND -- and it climbs from 0.62 nH at 0.55 mm to 3.29 nH at 0.20 mm as that stops happening. Snapping the mesh to the copper reaches the same place without the uniform cost: 3.04 nH, moving 1.6 % on the last refinement. FastHenry falls down its own series, 3.12 nH at 1.8 mm to 2.68 nH at 0.75 mm, because a filament grid that coarse cannot let the return current concentrate under a leg running 0.4 mm above it, which is most of what sets this loop, and it has settled there: the last refinement moved it 1.3 % and in the other direction. The figure quoted for FastHenry here is the converged end of that sweep, 0.75 mm at 1 MHz, not the production run's 1.2 mm grid; the production model's own frequency sweep falls about 3 % between 1 MHz and 100 MHz, which is the band the FDTD extraction sits in, so the comparison is fair to within a few per cent either way. Neither solver had been run to its own convergence before this.

What the device costs the model

The PEEC model shorts a conducting FET at its own pads and pays nothing for it. A full-wave model cannot: the short has to be a real piece of copper, and a strip 0.35 mm wide sitting 0.15 mm above a ground plane carries a partial inductance of its own. Halving its width doubles that term and leaves the loop alone, so L(w) = L₀ + k/w and the pair extrapolates to the ideal short: 3.177 nH at full width and 3.444 nH at half give 2.91 nH for the loop alone, the strip itself accounting for 0.27 nH. That is the number the two solvers can honestly be compared on.

Q12

The motor frame swings with the switch node

The four Ø3.2 mm motor mounts are NPTH — no copper, not a ground bond — so nothing on this board ties the motor's frame to board GND. The frame is left as a capacitive divider between the winding-to-frame capacitance and its own stray capacitance to the board, and it follows the switch node. Since everything here is driven by the edge, the sweep is run at both ends of the driver-impedance bracket of Q2.

Three things fall out of it. Left floating, the frame reaches 71 V peak against the 10 V criterion, though it carries almost no current, because there is nowhere for it to go. Bonding it with a long wire makes the voltage worse than a short one — 65 V against 29 V — because 20 nH resonates with C_wf and the frame overshoots. And nothing in the sweep is safe across all of it. Counting only the bonds that hold at every winding-to-frame capacitance — passing at one value of a quantity nobody has measured is not a fix — at the driver impedance the datasheet implies a strap 2 nH keeps the frame under 10 V, and at the strong-driver corner only 1 of 12 rows passes at all.

P8

Thermal, the optional phase

The design's thermal model is geometry.via_thermal(), geometry.thermal() and geometry.sink_needed(). Only the two numbers it leans on are re-solved here.

The via array comes out 1.16× the estimate — close enough that the design's number stands.

The lateral spreading on F.Cu alone, from the low-side source pads to the heatsink land at R > 29.2 mm, is 11.3 K/W. That is one layer of six and an upper bound on that path; the design's whole-stack estimate is 1.0 K/W and the other five layers conduct in parallel.

The conduction phase's own Joule numbers, at the 28.3 A peak: 0.741 W in the switch node, 0.3 W in the ground return, 0.024 W in the phase pour — against geometry.losses()'s 10.56 W total, of which 5.69 W is device conduction.

Method

What was solved with what, and what was checked first

There is no passwordless sudo on this machine, so nothing was installed with apt. FastHenry2 and FastCap2 were built from the FastFieldSolvers sources (both needed patching for a modern compiler: K&R declarations, -fcommon, and FastCap's own sbrk allocator, whose implicitly-declared pointers are truncated on 64-bit and segfault the solver). ngspice is driven through the libngspice.so.0 that KiCad installs, because there is no CLI. openEMS is built and run inside a container with only sim/ mounted.

Known-answer tests

Two of these are worth naming. The strip-over-plane case — exactly geometry.commutation_loop()'s PCB term — comes out at 0.487 nH in FastHenry and 0.506 nH in openEMS, against the closed form's 0.387 nH: the two solvers agree with each other to a few per cent and both sit above the formula, which ignores fringing and the return path. And the straight-wire test disagrees with the spec's own expected value: SPEC.md §5.4 quotes 17.4 nH, but its own formula with l = 20 mm and r = 0.5 mm gives 14.53 nH, which is what FastHenry returns.

The MOSFET model

ngspice's VDMOS has one shape parameter for C_gd and cannot be 32 pF at 40 V, integrate to 13 nC of Miller charge, and leave Q_g at 61 nC all at once. C_gd and C_ds are therefore charge-defined behavioural capacitors outside the primitive, solved from the datasheet's own specified points.

Switching times, as a check on the whole model

The toolchain as it ran

{
 "fasthenry": "/home/sequoia/opt/FastHenry2/bin/fasthenry",
 "fastcap": "/home/sequoia/opt/FastCap2/bin/fastcap",
 "ngspice": "/usr/lib/x86_64-linux-gnu/libngspice.so.0",
 "openems_image": "servodrive-openems:latest",
 "numpy": "2.3.5",
 "scipy": "1.18.1",
 "matplotlib": "3.10.7+dfsg1",
 "magpylib": "5.2.3",
 "shapely": "2.1.2",
 "meshio": "5.3.5",
 "skfem": "12.0.2",
 "pyamg": "5.3.0",
 "h5py": "3.16.0",
 "gmsh": "4.15.2",
 "pcbnew": "ok"
}

Extraction

The board is read with pcbnew into sim/work/geometry.json — zone fills, pad polygons at their own absolute angles, tracks, barrels with their layer spans — and every solver builds from that. Nothing here edits hardware/.

Scope

What this does not answer

• The RP2350 core buck (VREG_LX, 3.3 µH) and its spurs on +3V3A — out of scope by SPEC.md §4.
• USB and RS-485 signal integrity — out of scope.
• A motor FEA — there is no motor.
• Board B's own layout — none exists; it is modelled lumped.
• Thermal beyond the two numbers P8 re-solves — the via array's resistance and the lateral spread on F.Cu. There is no transient model and no heatsink.

And four kinds of number in here are bracketed rather than measured, because the part has not been chosen or the maker does not publish the figure: the EG2103's output impedance, the FET package's lead inductance, the DC-bias curve of the DC-link ceramics, and the TVSs' junction capacitance and forward resistance. Each is swept, and every result that depends on one says so. The first is the one that matters: it sets the edge rate, and the edge rate sets Q2, Q3, Q4's dV/dt and Q12.