Board S — the bulk cans

Why two cans are not enough, and what helps

• The ripple is fixed by the inverter. Three legs at m = 0.8 and 20 A RMS draw 12.4 A RMS of ripple from the DC link, mostly at 20 and 40 kHz. The cells’ ceramics are about 8 µF at 48 V — an ohm at 20 kHz — so the cans take all of it, and a little more, because the battery lead rings against them.
• Ratings are at 100 kHz and 105 °C. Every candidate datasheet that gives a frequency table takes 0.7 of the 100 kHz rating for 10–100 kHz. The part on the board, C2887236 (2.5 A), is good for about 1.75 A there.
• In parallel, the cans share by capacitance. At 20–40 kHz a 100 µF can is mostly reactance, so what a bank can carry is the ripple rating per microfarad of the part it is made of. A Ø10 100 µF part has 0.025–0.032 A/µF; a Ø6.3 22 µF part rated 2.6 A has 0.12. Six Ø6.3 cans hold 132 µF and 15.6 A of 100 kHz rating; two Ø10 cans hold 200 µF and 5.0 A.
• Mixed banks do not work. A Ø10 among Ø6.3s takes 5 A or more on its own: one Ø10 and four Ø6.3 carry 7.7 A per phase, less than three Ø8.
• Ceramics do not either. Twenty 10 µF/100 V 1210s are about 70 µF at 48 V; they take the cans from 6.4 to 4.4 A each, and 7.9 A per phase is where that stops.
• Bigger cans do not fit. A Ø12.5 × 17 220 µF part (3.5 A) would carry 7.8 A per phase in pairs, and no pocket on the board takes a Ø12.5.

The options that fit, in the board’s DC-link network

Each bank run through the simulation’s own P4 network (sim/phases/p4_dclink.py): the synthesised inverter current, the three cells’ ceramics at bias, the plane path P1 solved, the bus TVS and a 50 mΩ battery lead of 0.5, 1 or 2 µH, over the ceramic and ESR corners (18 cases). The bar is the phase current the bank carries continuously with every can inside its rating at the worst corner; the tick is the nominal case (typical ceramics, maximum ESR, 1 µH lead).

Every bank fits on the board except the ceramics, which were not placed: they stop at 7.9 A. Ripple per can (against its rating at 20–40 kHz), heat and the battery lead are the nominal case, with the worst of the 18 in brackets for the bus and the lead. Heat is I²·ESR at the datasheet’s maximum ESR. Costs are JLCPCB’s single-piece prices on 2026-09-28. The criterion for bus ripple is 3 V_pp at the drains.

Parts

From a sweep of JLCPCB’s catalogue for 80–100 V polymer and hybrid parts up to Ø12.5 (1,761 capacitors); 63 V is ruled out by the bus TVS’s clamp. No Ø10 at 80–100 V is rated over 3.2 A, and the hybrids are rated lower than the polymers.

What fits

Every spot on the outward face was tested with the placer’s own rules (placement_s.legal()) against the parts that cannot move: board A’s cells and CPU, their locked vias, the XT30, the header, the ports and the bucks. With the centre’s small parts free to go elsewhere, the outward centre has three pockets between the M3 heads, at 45, 135 and 315°. Each takes one Ø10 or Ø8, or two Ø6.3 side by side. The 45° pocket had no room for a Ø10 (phase A’s driver comes into it), which is why the board had two cans. The motor-facing face has 10.75 mm to the motor but is under the phase cells outside R 17, and inside it takes only parts under 1.5 mm.

Routing

Each bank was placed, generated from scratch (gen_boards.py --board s --force) and routed with the board’s own pipeline, several recipes side by side in scratch copies, then the targeted rip-ups that closed the last board’s last net. What it took for six cans:

• Placed first, the cans moved sixty parts — the buck modules 0.4 mm round C1002’s new lead, the bucks’ overflow caps, the LED 29 mm, the relay’s transceivers up to 24 mm — and the board no longer routed: 7–17 connections left, 6 after rip-ups. Five cans placed the same way left 10–11, three Ø8 11–22.
• Swapped into the board as built (placement_s._swap_bulk): the routed board’s placement with the two Ø10 cans, the six put in at the spots and turns that displace the fewest parts, and only those 16 placed again, each nearest where it was. Transceivers stay inside R 17.5: out in the ring one sat among phase A’s sense parts and could not reach the CPU. Three arrangements of the two displaced transceivers were routed; the one on the board puts port IN’s receiver at the top of the motor-facing centre and port OUT’s driver where port IN’s had been.
• The last net was the RP2350’s. The best routes stopped one or two short, always in the corridor from the CPU into the centre, where C1015’s leads and its VBUS finger now stand: EXP_GP24, XIN and RS485_OUT_TX took turns being the one left. What closed it was the maze making the RS-485 IN pair and the encoder’s CS and DO before the router (--first EN_12V,USB_VBUS,LIN_A,EXP_GP19,EXP_GP22,RS485_IN_DN_N,RS485_IN_DN_P,ENC_CS,ENC_DO), three left, and three targeted rip-ups: EXP_GP24, HIN_A, SWCLK.

Also clean: KiCad’s netlist export against schematic_s.nets(), the netlist checks, and deadcheck; the board carries exactly the eight pads of the four new cans more than before.